Assembly Hall of Shame Ranks Slowest CPU Instructions
The Assembly Hall of Shame project highlights extreme processor instruction latency, crowning the x86 fxrstor64 instruction as its current champion. Tested on an AMD Ryzen 7 5800H processor, the setup achieved a record-breaking delay of 198,002,498,236 cycles over 62 seconds. The benchmark demonstrates how PCIe fabric traffic contention can intentionally cripple single-instruction performance.
Key points
- The Assembly Hall of Shame project tracks the absolute floor of single-instruction performance rather than standard optimization.
- The x86 fxrstor64 instruction achieved the current record score of 198,002,498,236 cycles in a time of 62 seconds.
- Testing was conducted on an AMD Ryzen 7 5800H processor using a fleet of hammer cores to saturate the PCIe root complex with non-posted transactions.
- Honorable mentions include a spec-violating unaligned ymm0 load that disrupted System Management Mode.
While typical software engineering focuses on maximizing execution speed, the Assembly Hall of Shame project takes the inverse approach by searching for the absolute floor of single-instruction performance. The initiative highlights extreme latency bottlenecks in modern computing architectures through deliberate stress testing.
The project crowned the x86 fxrstor64 instruction as its current champion. Tested using an AMD Ryzen 7 5800H processor, the benchmark recorded a staggering delay of 198,002,498,236 cycles over a duration of 62 seconds. The test strategy involved loading a 512-byte FPU state from a high-latency memory-mapped I/O region in the PCIe fabric while simultaneously starving the fabric with a fleet of hammer cores executing tight 4-byte reads.
Additional entries include notable variations, such as a spec-violating unaligned ymm0 load that forced non-posted dword transactions from stalled graphics processing unit registers to bypass standard System Management Mode designs. Project rules dictate that evaluated instructions must be uninterrupted, prohibiting instructions like rep movs or pause while excluding trap handlers from timing measurements.
Sources
The WireByte editorial team synthesises technology news from multiple primary sources, verifies the facts, and links every source. Articles are produced with AI assistance and reviewed under our editorial policy.